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E2L0035-17-Y1 Semiconductor
Semiconductor MSM548333
DESCRIPTION
This version: Jan. 1998 MSM548333 Previous version: Dec. 1996
240,384-Word 8-bit + 240,384-Word 4-bit Triple Port type Field Memory
The MSM548333 is a high performance double triple-port type 2.88-Mbit, 768 bits 313 lines (8 + 4), Field Memory for Y-C separation signal control. The MSM548333 has two memory plain blocks: Y area has 8 plains and C area has 4 plains. Each plain contains 768 313 bits. Each plain has one input port and two output ports. Access is done line by line. The line address must be set each time a line is changed. The MSM548333 is especially designed for high performance digital cameras, TVs, VTRs and Multimedia applications which require special operations such as time-base correction, noise reduction and other digital techniques. The MSM548333 is not designed for high end use in such applications as medical systems, professional graphics systems which require long term picture storage, data storage systems and others. More than two MSM548333s can be cascaded directly without any delay devices between them. Cascading MSM548333s provides larger capacity and longer delay. X and Y serial address input enables random initial address setting of serial access in a page. Other than the random address setting, MSM548333 has several types of address set modes such as line hold, address jump to initial address and line increment. For example, address jump to initial X address and line increment enable block access. Self refresh function releases the MSM548333 from being applied external refresh control clocks even though it contains dynamic type memory cells. Input enable control or IE pin enables write mask function.
FEATURES
* Configuration 6-port configuration Y area: 768 313 8-bit configuration 1 (serial write port) 768 313 8-bit configuration 2 (serial read port) C area: 768 313 4-bit configuration 1 (serial write port) 768 313 4-bit configuration 2 (serial read port) * Line by line access. * X and Y serial address inputs for random serial initial bit address * Asynchronous operation * Serial read and write cycle times Read cycle: 30 ns min. Write cycle: 50 ns min. * Low operating supply voltage: 3.3 V 0.3 V * Self-refresh. * Various address reset mode for picture processing * Write mask by IE. * Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product : MSM548333TS-K)
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
98 RADE2/RX 79 WADE/RX 92 RYADY2 91 RYADC2
RR2/TR 1 REC2/RY 2 RCLKC2 3 NC 4 REY2/RY 5 RADE1/RX 7 RXINC1 8 NC 9
RCLKY2 6
RR1/TR 10 RE1/RY 11 NC 12 RCLK 13 NC 14 VSS 15 VSS 16 VSS 17 DOY1/0 18 DOY1/1 19 DOY1/2 20 DOY1/3 21 NC 22 VCC 23 DOY1/4 24 DOY1/5 25

99 RXINC2 97 TEST 100 NC
MSM548333
83 WE/WY
78 DINY/0
77 DINY/1
96 RXAD1
81 WR/TR
80 WXINC
95 RYAD1
93 RXAD2
86 WYAD
90 WXAD
85 WCLK
88 VCC
87 VCC
82 NC
76 NC 75 DINY/2 74 DINY/3 73 DINY/4 72 NC 71 DINY/5 70 DINY/6 69 DINY/7 68 DINC/0 67 NC 66 DINC/1 65 DINC/2 64 NC 63 DINC/3 62 VCC 61 VSS 60 NC 59 VSS 58 DOC2/0 57 DOC2/1 56 DOC2/2 55 NC 54 DOC2/3 53 VCC 52 DOC1/0 51 DOC1/1
94 NC
89 NC
NC 26
DOY1/6 27
DOY1/7 28
VSS 29
VSS 30
DOY2/0 31
DOY2/1 32
DOY2/2 33
NC 34
DOY2/3 35
VCC 36
VCC 37
VCC 38
NC 39
VCC 40
DOY2/4 41
NC 42
84 IE
DOY2/5 43
DOY2/6 44
DOY2/7 45
VSS 46
VSS 47
DOC1/3 48
DOC1/2 49
100-Pin Plastic TQFP
NC 50
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Semiconductor
MSM548333
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Pin Name RR2/TR REC2/RY RCLKC2 NC REY2/RY RCLKY2 RADE1/RX RXINC1 NC RR1/TR RE1/RY NC RCLK NC VSS VSS VSS DOY1/0 DOY1/1 DOY1/2 DOY1/3 NC VCC DOY1/4 DOY1/5
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pin Name NC DOY1/6 DOY1/7 VSS VSS DOY2/0 DOY2/1 DOY2/2 NC DOY2/3 VCC VCC VCC NC VCC DOY2/4 NC DOY2/5 DOY2/6 DOY2/7 VSS VSS DOC1/3 DOC1/2 NC
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Pin Name DOC1/1 DOC1/0 VCC DOC2/3 NC DOC2/2 DOC2/1 DOC2/0 VSS NC VSS VCC DINC/3 NC DINC/2 DINC/1 NC DINC/0 DINY/7 DINY/6 DINY/5 NC DINY/4 DINY/3 DINY/2
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pin Name NC DINY/1 DINY/0 WADE/RX WXINC WR/TR NC WE/WY IE WCLK WYAD VCC VCC NC WXAD RYADC2 RYADY2 RXAD2 NC RYAD1 RXAD1 TEST RADE2/RX RXINC2 NC
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MSM548333
Pin Name RCLK RE1/RY DOY1/0 - 7 DOC1/0 - 3 RR1/TR RXINC1 RADE1/RX RXAD1 RYAD1 RR2/TR RXINC2 RADE2/RX RXAD2 RYADY2 RCLKY2 REY2/RY DOY2/0 - 7 RYADC2 RCLKC2 REC2/RY DOC2/0 - 3 WCLK WE/WY DINY/0 - 7 DINC/0 - 3 WR/TR WXINC WADE/RX WXAD WYAD IE VCC VSS TEST
Function Address Setting Cycle
Y1, C1, Y2 and C2 Read Ports X and Y Serial Address Strobes Y1 and C1 Read Ports, Y Address Reset -- -- Y1 and C1 Read Ports, Address Reset Mode Enable Y1 and C1 Read Ports, X Address Increment Y1 and C1 Read Ports, X and Y Address Input Enable Y1 and C1 Read Ports, X Address Reset Y1 and C1 Read Ports, X Serial Address Data Y1 and C1 Read Ports, Y Serial Address Data Y2 and C2 Read Ports, Address Reset Mode Enable Y2 and C2 Read Ports, X Address Increment Y2 and C2 Read Ports, X and Y Address Input Enable Y2 and C2 Read Ports, X Address Reset Y2 and C2 Read Ports, X Serial Address Data Y2 Read Port, Y Serial Address Data -- Y2 Read Port, Y Address Reset -- C2 Read Port, Y Serial Address Data -- C2 Read Port, Y Address Reset -- Y and C Write Ports, X and Y Serial Address Strobes Y and C Write Ports, Y Address Reset -- Y and C Write Ports, Address Reset Mode Enable Y and C Write Ports, X Address Increment Y and C Write Ports, X and Y Address Input Enable Y and C Write Ports, X Address Reset Y and C Write Ports, X Serial Address Data Y and C Write Ports, Y Serial Address Data -- Input Enable Power Supply Voltage (3.3 V) Ground (0 V) Connect to Power Supply Voltage (3.3 V) Y1 and C1 Read Ports, Read Enable Y1 Read Port, Data Output C1 Read Port, Data Output -- -- -- -- -- -- -- -- -- -- Y2 Read Port, Serial Read Clock Y2 Read Port, Read Enable Y2 Read Port, Data Output -- C2 Read Port, Serial Read Clock C2 Read Port, Read Enable C2 Read Port, Data Output Y and C Write Ports, Serial Write Clock Y and C Write Ports, Write Enable Y Write Port, Input Data C Write Port, Input Data Y and C Write Ports, Write Data Transfer -- -- -- --
Serial Read/Write Cycle
Y1 and C1 Read Ports, Serial Read Clock
Notes:
1. Same power supply voltage level must be provided to every VCC pin. Same ground voltage level must be provided to every VSS pin. 2. Connect the TEST pin to the power supply. 3. NC must be opened. Don't connect to anything electrically. 4/42
Semiconductor
BLOCK DIAGRAM
WCLK WE/WY DINY/0 to DINY/7 DINC/0 to DINC/3 WXINC WADE/RX WCLK WE/WY WYAD WR/TR WXAD Refresh Controller 12 Write Buffer IE
Write Register iY j
Write Register iC j
Write Address Control RXINC1 RR1/TR RXAD1 Read Address Control iY1/C1 j RXINC2 RR2/TR RXAD2 Read Address Control iY2 j Read Address Control iC2 j 8 DOY1/0 to DOY1/7
DOUT Buffer-1 8 bits DOUT Buffer-1 4 bits
RADE1/RX RCLK RE1/RY RYAD1
Memory Cell Array Memory Controller
Y-Region 768 313 8 bits
C-Region 768 313 4 bits
RADE2/RX RCLK REY2/RY RYADY2 RCLK REC2/RY RYADC2
Read Register iY2 j
Read Register iY1 j
Read Register iC1 j
Read Register iC2 j
4 DOC1/0 to DOC1/3
8 DOY2/0 to DOY2/7
DOUT Buffer-2 8 bits
DOUT Buffer-2 4 bits
4
MSM548333
DOC2/0 to DOC2/3
RCLKY2
RE1/RY REY2/RY
RCLK REC2/RY
RCLKC2
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MSM548333
PIN FUNCTION (Note : Y1 = "port-1 of Y area", Y2 = "port-2 of Y area", C1 = "port-1 of C area", C2 = "port-2 of C area "
READ RELATED RCLK : Read Clock for Y1 and C1, Common Read Address Strobe Clock RCLK is the read control clock input for Y1 and C 1. Synchronized with RCLK's rising edge, serial read access from Y1 and C1 is executed when RE1/RY is high. (Note that the write port has one port, Y and C, but the read port has dual ports, Y1 and C1 plus Y2 and C2. Y1 and C1 are controlled by the common read clock RCLK. But Y2 and C2 are controlled by separated read clocks, RCLKY2 and RCLKC2, asynchronously.) The internal counter for the serial read address is incremented automatically on the rising edge of RCLK. In a read address set cycle, all the read address bits which were input from each RXAD1, RYAD1, RXAD2, RYADY2, and RYADC2 pins are stored into internal address registers synchronized with RCLK. In this address set cycle, RADE1/RX and RADE2/RX must be held high and the RR1/ TR and RR2/TR must be held low. In the read address reset cycle, various read address reset modes can be set synchronously with RCLK. These reset cycles work to replace complicated serial address control which requires many RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates memory access. RE1/RY : Read Enable for Y1 and C1/Read Y Address Reset Logic Function RE1/RY is a dual function control input. RE1, one of the two functions of RE1/RY, is read enable. RE1 enables or disables both internal read address pointers and data-out buffers of Y1 and C1. When RE1/RY is high, the internal read address pointer for Y1 and C1 is incremented synchronously with RCLK. When RE1/RY is low, even if the RCLK is input, the internal read address pointer is not incremented. RY, the second function of RE1/RY, performs a function for setting the read Y address (or bit address in a certain line) reset mode in Y1 and C1. In a read address reset mode cycle, as defined by RR1/TR being high, RY works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read". In the address reset cycle, when RE1/RY level is low, each Y1and C1 internal read Y address is reset to 0. When RE1/RY is high, each Y1 and C1 internal read Y address is reset to the respective address which was set in the previous read address set cycle. DOY1/0-7 : Data-Outs for Y1 DOY1/0-7 are serial data-outs for Y1. Each corresponding data out buffer' impedance is controlled by RE1/RY. DOC1/0-3 : Data-Outs for C1 DOC1/0-3 are serial data-outs for C1. Each corresponding data out buffer' impedance is controlled by RE1/RY. RR1/TR : Read Reset for Y1 and C1 RR1/TR is a read reset control input for Y1 and C1. Read address reset modes are defined when RR1/ TR level is high according to the "FUNCTION TABLE for read". RXINC1 : Read X Address Increment for Y1 and C1 RXINC1 is a read X address (or line address) increment control input for Y1 and C1. In the read address reset cycle, defined by RR1/TR high, the common X address (or line address) for Y1 and C1 is incremented by RXINC1.
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MSM548333
RADE1/RX : Read Address Enable for Y1 and C1/Read X Address Reset Logic Function RADE1/RX is a dual function control input. RADE1, one of the two functions of RADE1/RX, is a read address enable input for Y1 and C1. In the read address set cycle, defined by RR1/TR low, X address (or line address) and Y address (or bit address in a certain line) input from the RXAD1 pin and RYAD1 pin are latched into internal read X address register and Y address register, respectively synchronously with RCLK. RX, the second function of RADE1/RX, works as an element to set read X address (or line address) reset mode. In an address reset mode cycle, defined by RR1/TR level high, RX works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read". RXAD1 : Read X Address for Y1 and C1 RXAD1 is a read X address (or line address) input for Y1 and C1. RXAD1 specifies the line address. 9 bits of read X address data are input serially from RXAD1. RYAD1 : Read Y Address for Y1 and C1 RYAD1 is a read Y address (or bit address in a certain line) input for Y1 and C1. RYAD1 specifies the first bit address of consecutive serial read data in the line whose line address is defined by the X read address from RXAD1. 10 bits of Y address data are input serially from RYAD1. RR2/TR : Read Reset for Y2 and C2 RR2/TR is a read reset control input for Y2 and C2. Read address reset modes for Y2 and C2 are defined when RR2/TR level is high based on the "FUNCTION TABLE for read". RXINC2 : Read X Address Increment for Y2 and C2 RXINC2 is a read X address (or line address) increment control input for Y2 and C2. In the read address reset cycle, defined by RR2/TR high, the common read X address (or line address) for Y2 and C2 is incremented by RXINC2. RADE2/RX : Read Address Enable for Y2 and C2/Read X Address Reset Logic Function RADE2/RX is a dual function control input. RADE2, one of the two functions of RADE2/RX, is a read address enable input for Y2 and C2. In the read address set cycle, defined by RR2/TR high, the read X address (or line address) and the read Y address (or bit address in a certain line), which are input from the RXAD2, RYADY2 and RYADC2 pins, are latched into internal read X address register and read Y address register, respectively, synchronously with RCLK. RX, the second function of RADE2/RX, performs a function for setting the read X address (or line address) reset mode. In a read address reset mode cycle, defined by RR2/TR level high, RX works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read". RXAD2 : Read X Address for Y2 and C2 RXAD2 is a read X address (or line address) input for Y2 and C2. RXAD2 specifies the line address. 9 bits of X address data is input serially from RXAD2. RYADY2 : Read Y Address for Y2 RYADY2 is a read Y address (or bit address in a certain line) input for Y2. RYADY2 specifies the first bit address of serial read data in the line whose line address is specified by the X address RXAD2. 10 bits of Y address data are input serially from RYADY2.
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Semiconductor
MSM548333
RCLKY2 : Read Clock for Y2 RCLKY2 is a read control clock input for Y2. (Note that there is RCLKC2 for C2.) Synchronized with RCLKY2's rising edge, the serial read access from Y2 is executed when REY2/RY is high. REY2/RY : Read Enable for Y2/Read Y Address Reset Logic Function for Y2 REY2/RY is a dual function control input. REY2, one of the two functions of REY2/RY, enables or disables both internal read address pointers and data-out buffers of Y2. When REY2/RY is high, the internal read address pointer for Y2 is incremented synchronously with RCLKY2. When REY2/RY is low, even if RCLKY2 is input, the internal read address pointer is not incremented. RY, the second function of REY2/RY, works as an element to set read Y address (or bit address in a certain line) reset mode. In a read address reset mode cycle, defined by RR2/TR high, RY works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read". In the read address reset cycle, when REY2/RY is low, the internal read Y address for Y2 is reset to 0. When REY2/RY is high, the internal read Y address for Y2 is reset to the address which was set in the previous address set cycle. DOY2/0-7 : Data-Outs for Y2 DOY2/0-7 are serial data-outs for Y2. Each corresponding data-out-buffer' impedance is controlled by REY2/RY. RYADC2 : Read Y Address for C2 RYADC2 is a read Y address (or bit address in a certain line) input only for C2. RYADC2 specifies the first bit address of serial read data in the line whose line address is specified by RXAD2. 10 bits of Y address data are input serially from RYADC2. RCLKC2 : Read Clock for C2 RCLKC2 is a read control clock input for only C2. (Note that there is RCLKY2 for Y2.) Synchronized with RCLKC2, serial read access from C2 is executed when REC2/RY is high. REC2/RY : Read Enable for C2/Read Y Address Reset Logic Function for C2 REC2/RY is a dual function control input. REC2, one of the two functions of REC2/RY, enables or disables both internal read address pointers and data-out buffers for C2. When REC2/RY is high, the internal read address pointer for C2 is incremented synchronously with RCLKC2. When REC2/RY is low, even if RCLKC2 is input, the internal read address pointer is not incremented. RY, the second function of REC2/RY, performs a function for setting the read Y address (or bit address in a certain line) reset mode. In an address reset mode cycle, defined by RR2/TR high, RY works as one of inputs which form several read reset logic as shown in the "FUNCTION TABLE for read". In the read address reset cycle, when REC2/RY is low, the internal read Y address for C2 is reset to 0. When REC2/RY is high, the internal read Y address for C2 is reset to the address which was set in the previous read address set cycle. DOC2/0-3 : Data-Outs for C2 DOC2/0-3 are serial data-outs for C2. Each corresponding data out buffer' impedance is controlled by REC2/RY.
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Semiconductor WRITE RELATED
MSM548333
WCLK : Write Clock for Y and C WCLK is a write control clock input for Y and C ports. Synchronized with WCLK's rising edge, serial write access into Y and C ports is executed when WE/WY is high and IE is high. (Note that the read port is dual port, Y1 and C1 + Y2 and C2, but write port has only one port, Y + C. X8 of Y and X4 of C inputs are controlled by a common WCLK, that is, in the write port, the MSM548333 is controlled as a X12 FRAM.) According to WCLK clocks, the internal counter for the serial address is incremented automatically. In a write address set cycle, all the write addresses which were input from WXAD and WYAD are stored into internal address registers synchronously with WCLK. In this address set cycle, WADE/ RX must be held high and WR/TR must be held low. In the write address reset cycle, various write address reset modes can be set synchronously with WCLK. These reset cycles replace complicated serial address control with simple reset cycle control which requires only one WCLK cycle. It greatly facilitates memory access. WE/WY : Write Enable for Y and C/Write Y Address Reset Logic Function WE/WY is a dual function control input. WE, one of the two functions of WE/WY, is write enable. WE enables or disables both internal write address pointers and data-in buffers of Y and C. When WE/WY is high, the internal write address pointer for Y and C is incremented synchronously with WCLK. When WE/WY is low, even if WCLK is input, the internal write address pointer is not incremented. WY, the second function of WE/WY, performs a function for setting the write Y address (or bit address in a certain line) reset mode in Y and C. In a write address reset mode cycle, defined by WR/ TR high, WY works as one of inputs which form several write reset logic as shown in the "FUNCTION TABLE for write". In the address reset cycle, when WE/WY level is low, each Y and C internal write Y address is reset to 0. When WE/WY is high, each Y and C internal write Y address is reset to the respective address which was set in the previous write address set cycle. DINY/0-7 : Data-Ins for Y DINY/0-7 are serial data-ins for Y. Each corresponding data-in-buffer is masked by IE. DINC/0-3 : Data-Ins for C DINC/0-3 are serial data-ins for C. Each corresponding data-in-buffer is masked by IE. WR/TR : Write Reset for Y and C WR/TR is a write reset control input for Y and C. Write address reset modes are defined when WR/ TR level is high according to the "FUNCTION TABLE for write". WXINC : Write X Address Increment for Y and C WXINC is a write X address (or line address) increment control input for Y and C. In the write address reset cycle, defined by WR/TR high, the common write X address (or line address) for Y and C is incremented by WXINC. WADE/RX : Write Address Enable for Y and C/Write X Address Reset Logic Function WADE/RX is a dual functional control input. WADE, one of the two functions of WADE/RX, is a write address enable input for Y and C. In the write address reset cycle, defined by WR/TR high, X address (or line address) and Y address (or bit address in a certain line) input from WXAD and WYAD are latched into internal write X address register and Y address register.
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Semiconductor
MSM548333
WXAD : Write X Address for Y and C WXAD is a write X address (or line address) input for Y and C. WXAD specifies line address. 9 bits of write X address data are input serially from WXAD. WYAD : Write Y Address for Y and C WYAD is a read Y address (or bit address in a certain line) input for Y and C. WYAD specifies the first bit address of consecutive serial write data in the line whose line address is defined by X write address from WXAD. 10 bits of write Y address data are input serially from WYAD. IE : Input Enable for Y and C IE is an input enable which controls the write operation. When IE is high, the input operation is enabled. When IE is low, the write operation is masked. When WE/WY signal is high, and IE low, the internal serial write address pointer is incremented on the rising edge of WCLK without actual write operations. This function facilitates picture in picture function in a TV system.
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Semiconductor
MSM548333
OPERATION MODE
Write 1. Write operation Before the write operation begins, X address (or line address) and Y address (or bit address in the line specified by the X address) must be input to set the initial bit address for the following serial write access. When WE/WY and IE are high, a set of serial 12-bit -width write data on DINY/0-7 and DINC/0-3 is written into write registers attached to the DRAM memory arrays temporarily on the rising edge of WCLK. Following 12-bit-width serial input data is written into the memory locations in the write register designated by an internal write address pointer which is advanced by WCLK. This enables continuous serial write on a line. When write clock WCLK and read clock RCLK are tied together and are controlled by a common clock or CLK, more than two MSM548333s can be cascaded directly without any delay devices between the MSM548333s because the read timing is delayed by one CLK cycle to the write timing. When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the written data in the write registers to the corresponding memory cells in the DRAM memory arrays. 2. Write address pointer increment operation The write address pointer is incremented synchronously with WCLK when WE/WY is high. When the write address pointer reaches the last address of a line, it stops at the last address and no address increment occurs.
Relationship between the WE/WY and IE input levels, Write Address pointer, and data input status WCLK Rise WE/WY H H L IE H L -- Internal Write Address Pointer Incremented Stopped Data Input Inputted Not Inputted
When WE/WY and IE are high, the write operation is enabled. If IE level goes low while WCLK is active, the write operation is halted but the write address pointer will continue to advance. That is, IE enables a write mask function. When WE/WY goes low, the write address pointer stops without WCLK. Read (Here, "port-1 of Y area" is Y1, "port-2 of Y area" is Y2, "port-1 of C area" is C1, "port-2 of C area" is C2.) 1. Read operation MSM548333 has dual read ports, port-1 for Y and C memory areas and port-2 for Y and C memory areas. Note that the read of Y1 and C1 are controlled by a common control clock at the same time. But the read of Y2 and C2 are controlled by separate sets of control clocks, independently. Before the read operation begins, the X address (or line address) and Y address (or bit address in the line specified by the X address) must be input for setting initial bit address for the following serial read access. When RE1/RY is high, a set of serial 12-bit-width read data on DOY1/0-7 pins and DOC1/ 0-3 pins is read from read registers attached to DRAM memory arrays on the rising edge of RCLK. When REY2/RY is high, a set of serial 8-bit-width read data on DOY2/0-7 pins is read from read registers attached to DRAM memory arrays on the rising edge of RCLKY2. 11/42
Semiconductor
MSM548333
When REC2/RY is high, a set of 4-bit-width serial read data on DOC2/0-3 is read from the read registers attached to DRAM memory arrays on the rising edge of RCLKC2. Each access time is specified by the rising edges of RCLK, RCLKY2 and RCLKC2. 2. Read address pointer increment operation There are three separate pointers for dual port serial read operation. The first one is the read pointer for Y1 and C1 which is incremented by RCLK when RE1/RY is high. The second one is the read pointer for Y2 which is incremented by RCLKY2 when REY2/RY is high. The third one is the read pointer for C2 which incremented by RCLKC2 when REC2/RY is high. When each read address pointer reaches the last address of a line, it stops at the last address and no address increment occurs. Initial Address Setting (Write/Read Independent) Any read operations are prohibited in the read initial address set period. Similarly, any write operations are prohibited in the write initial address set period. Note that read initial address set and write initial address set can occur independently. Similarly, read access can be achieved independently from write initial address set period and write access can be achieved independently from read initial address set cycles. 1. Write address setting During a write, MSM548333 has one write address enable input, WADE/RX. Note that there are two read address enable inputs for read. WADE/RX enables Y and C initial read address inputs. When WADE/RX is high, 9 bits of serial X address (or line address) for Y and C and 10 bits of serial Y address (or bit address in the line specified by the X address) for Y and C are input in parallel from WXAD and WYAD respectively. The operations above enable selection of specific lines randomly and enables the start of serial write access synchronized with write clock WCLK. Address for each line must be input between each line access. In other words, MSM548333's write is achieved in a "line by line" manner. Any write operations are prohibited in the initial write address set periods. Y and C Serial write input enable time tSWE must be kept for starting a serial write just after the initial write address set period. 2. Read address setting During a read, MSM548333 has two read address enable inputs, RADE1/RX and RADE2/RX. RADE1/RX enables Y1 and C1 initial read address inputs. Similarly, RADE2/RX enables Y2 and C2 initial read address inputs. When RADE1/RX is high, 9 bits of serial X address (or line address) for Y1 and C1 and 10 bits of serial Y address (or bit address in the line specified by the X address) for Y1 and C1 are input in parallel from RXAD1 and RYAD1, respectively. Note that the X and Y address inputs when RADE1/RX is high are for Y1 and C1. When RADE2/RX is high, 9 bits of serial X address (or line address) for Y2 and C2 is input from RXAD2. In the same period, 10 bits of serial Y address (or bit address in the line specified by the X address) for Y2 is input from RYADY2 pin and another 10 bits of serial Y address (or bit address in the line specified by the same X address input from RXAD2) for C2 is input from RYADC2 pin. Note that the X address input here is for both Y2 and C2 and the two sets of Y address inputs from RYADY2 and RYADC2 are for Y2 and C2, respectively. That is, MSM548333 can't set separate line addresses in Y2 and C2 but can set separate initial bit address in Y2 and C2 on the specified lines by the common line address. The operations above enable selection of specific lines randomly and enables the start of serial read access synchronized with read clocks, RCLK for Y1 and C1, RCLKY2 for Y2 and RCLKC2 for C2. Address for each line must be input between each line access. In other words, 12/42
Semiconductor
MSM548333
MSM548333's read operation is achieved in "line by line" manner. Any read operations are prohibited in the initial read address set periods. Serial read operations for Y1 and C1, and also Y2 and C2, are prohibited while RADE1/RX is high. Similarly, serial read operations for Y1 and C1, and also Y2 and C2, are prohibited while RADE2/RX level is high. Y1 and C1 Serial read port enable time tSRE1, Y2 serial read port enable time tSREY2 and C2 serial read port enable time tSREC2 must be kept for starting a serial read just after the initial read address set period. Initial Address Reset Modes (Write/Read Independent) The initial address reset modes replace complicated read or write initial address settings with simple reset cycles. Initial address reset modes are selected by RR/TR high during read and WR/TR high during write. As in normal read or write address settings, any read operations are prohibited in the read address reset cycles. Similarly, any write operations are prohibited in the initial write address reset cycles. Note that read initial address reset and write initial address reset can occur independently. Similarly, read access can be achieved independently from write initial address reset cycles and write access can be achieved independently from read initial address reset cycles. Input addresses are stored into address registers which are connected with address counter which controls address pointer operation. In the serial access operation, the input address into the address registers are kept. Serial write data input enable time tSWE, Y1 and C1 read port read enable time tSRE1, Y2 serial read port read enable time tSREY2, C2 serial read port read enable time tSREC2 must be kept for starting serial read or write just after the initial read or write address reset cycles. Note that all the read ports' initial address reset must occur with the same timing. 1. Original address reset No.1 - "X, Y address counter reset" By the "Original address reset No.1" logic which is composed by a combination of control input' levels, the address counter is reset to (0,0), and then, the address pointer is initialized to (0,0). Reference the "FUNCTION TABLE" for read and write shown later. After the reset mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit address on the line is (0,0). The address counter is reset by this reset mode but the address register, which stored input address in the previous address reset cycle or address set cycle, is not reset. The non-initialized address can be used as a preset address in "address jump reset" mode. When the address register must be reset, choose "address register reset" mode. 2. Original address reset No.2 - "X,Y address register reset" By the "Original address reset No.2" logic, the address register is reset, and then, the address counter and address pointer are initialized to address (0,0) automatically. After the reset mode, serial access starts from the address (0,0) : the line address is "0" and the initial bit address on the line is (0,0) Both address register and address counter are reset to (0,0) and the stored initial address in the previous address reset cycle or address set cycle is cleared by this "address register reset". Once the reset mode is selected, the reset address (0,0) is stored in the address register as a preset address until next initial address set or reset operation. The address can be used as a preset address in the "address jump reset" mode. Note that REY2/RY and REC2/C2 must be both "L" at the same time when the "address register reset" is selected. REY2/RY = "L" and REC2/RY = "H" or REY2/RY = "H" and REC2/ RY = "L" are prohibited. 3. Original address reset No.3 - Y address counter reset" By the "Original address reset No.3" logic, the Y address register is reset, and then, address 13/42
Semiconductor
MSM548333
pointer for the line access is initialized to Y address (0). The X address Xi which specifies a certain line address is one which was stored in the X address register in the previous address reset or address set cycle. After the reset mode, serial access starts from the address (Xi,0) : line address is "Xi" and initial bit address on the line is (0). The Y address counter is reset by this reset mode but the Y address register, which stored the input initial Y address in the previous address reset cycle or address set cycle, is not reset. The non-initialized Y address can be used as a preset Y address in the "address jump reset" mode. 4. Line increment reset No.1 - "X address counter increment and Y address counter reset" By the "Line increment reset No.1" logic, the X address counter is incremented by one from the current X address and Y address is reset to address (0). That is, by the reset mode, serial access from the Y = (0) on the next line is enabled. 5. Line increment reset No.2 - "X address counter increment reset and Y address counter initialize" By the "Line increment reset No.2" logic, the X address counter is incremented by one from the current X address and Y address is initialized to the Y address set in the previous address set cycle. This enables block access on the screen. 6. Line hold reset No. 1 (1) operation When a predetermined input level is set during the reset setting cycle, access is executed starting from the first word on the current line. 7. Line hold (2) operation When a predetermined input level is set during the reset setting cycle, access is executed starting from the word address on the current line which is initialized. 8. Address jump operation When a predetermined input level is set during the reset setting cycle, a jump may be caused to the initialized line or word address. In the case of a read, set the same level in the Y2 and C2 regions for this operation. Note : During one reset setting cycle, a plurality of resets cannot be set.
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Semiconductor
MSM548333
Power ON Power must be applied to RCLK, RCLKY2, RCLKC2, RE1/RY, REY2/RY, REC2/RY and WE/WY input signals to pull them "Low" before or when the VCC supply is turned on. After power-up, the device is designed to begin proper operation in at least 200 ms after VCC has reached the specified voltage. After 200 ms, a minimum of one line dummy write operation and read operation is required according to the address setting mode, because the read and write address pointers are not valid after power-up. New Data Read Access In order to read out "new data', the delay between the beginning of a write address setting cycle and read address setting cycle must be at least two lines. Old Data Read Access In order to read out "old data", the delay between the beginning of a write address setting cycle and read address setting cycle must be more than 0 but less than a half line.
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Semiconductor
MSM548333
FUNCTION TABLE
1. Write
Mode No. 1 2 3 4 5 6 7 8 Address Setting Mode -- Description of Operation Write Transfer Reset (1) Reset (2) (Note) WR/TR H H H H H H H H L WXINC L L H H H L L H L WE/WY L L L L H H H H L WADE/ Internal Address RX Pointer L H H L L H L H H X and Y cleared to (0, 0) X and Y cleared to (0, 0) X set and Y cleared to (Xn + 1, 0) X and Y set to (Xn +1, Yi) X cleared and Y set to (0, Yi) X and Y set to (Xn, Yi) X and Y set to (Xi, Yi) X and Y set
Address Reset Mode
Line Increment (1) Line Increment (2) Reset (3) Line Hold (2) Address Jump First Address Setting
Note : When Address reset mode No. 3 is executed, the address X and Y which are set previously will be cleared. For write, Line hold (1) is not provided.
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Semiconductor 2. Read
Description of Operation Line Hold (1) Reset (1) Reset (2) (Note)
MSM548333
Mode
No. 1 2 3 4 5 6 7 8
RR*/TR H H H H H H H H L
RXINC* L L H H H L L H L
RE*/RY L L L L H H H H L * *
RADE* Internal Address /RX Pointer L H H L L H L H H X set and Y cleared to (Xn, 0) X and Y cleared to (0, 0) X and Y cleared to (0, 0) X set and Y cleared to (Xn + 1, 0) X and Y set to (Xn + 1, Yi) X cleared and Y set to (0, Yi) X and Y set to (Xn, Yi) X and Y set to (Xi, Yi) X and Y set
Address Reset Mode
Line Increment (1) Line Increment (2) Reset (3) Line Hold (2) Address Jump First Address Setting
Address Setting Mode
--
RR*/TR : RR1/TR, RR2/TR RE*/RY : RE1/RY, REY2/RY, REC2/RY
RXINC* RADE*/RX
: RXINC1, RXINC2 : RADE1/RX, RADE2/RX
* Set the same level in the Y2 and C2 regions. Note : When address reset mode No. 3 is executed, the addresses X and Y which are set previously will be cleared.
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Semiconductor
MSM548333
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Pin Voltage Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Condition Ta = 25C, with respect to VSS Ta = 25C Ta = 25C -- -- Rating -0.5 to 4.6 V 50 mA 1W 0 to 70C -55 to 150C
Recommended Operating Conditions
(Ta = 0 to 70C) Parameter Power Supply Voltage Power Supply Voltage "H" Input Voltage "L" Input Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.1 -0.5 Typ. 3.3 0 VCC 0 Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
DC Characteristics
(VCC = 3.0 to 3.6 V, Ta = 0 to 70C) Parameter "H" Output Voltage "L" Output Voltage Input Leakage Current Output Leakage Current Power Supply Current (During Operation) Power Supply Voltage (During Standby) Symbol VOH VOL ILI ILO ICC1 ICC2 Condition IOH = -0.1 mA IOL = 0.1 mA 0 < VI < VCC + 1 Other input voltage 0 V 0 < VO < 3.6 min. cycle Input pin = VIL/VIH Min. 2.2 -- -10 -10 -- -- Max. -- 0.7 10 10 50 10 Unit V V mA mA mA mA
Capacitance
(Ta = 25C, f = 1 MHz) Parameter Input Capacitance Output Capacitance Symbol CI CO Max. 7 7 Unit pF pF
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Semiconductor AC Characteristics (1/4)
MSM548333
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter WCLK Cycle Time WCLK "H" Pulse Width WCLK "L" Pulse Width Serial Write Address Input Active Setup Time Serial Write Address Input Active Hold Time Serial Write Address Input Inactive Hold Time Serial Write Address Input Inactive Setup Time Write Transfer Instruction Setup Time Write Transfer Instruction Hold Time Write Transfer Instruction Inactive Hold Time Write Transfer Instruction Inactive Setup Time Serial Write X Address Setup Time Serial Write X Address Hold Time Serial Write Y Address Setup Time Serial Write Y Address Hold Time Serial Write Data Input Enable Time Write Instruction Setup Time Write Instruction Hold Time Write Instruction Inactive Hold Time Write Instruction Inactive Setup Time IE Enable Setup Time IE Enable Hold Time IE Disable Hold Time IE Disable Setup Time Input Data Setup Time Input Data Hold Time WR/TR-WCLK Active Setup Time WR/TR-WCLK Active Hold Time WR/TR-WCLK Inactive Hold Time WR/TR-WCLK Inactive Setup Time WXINC-WCLK Active Setup Time WXINC-WCLK Active Hold Time WXINC-WCLK Inactive Hold Time WXINC-WCLK Inactive Setup Time WADE/RX-WCLK Active Setup Time WADE/RX-WCLK Active Hold Time WADE/RX-WCLK Inactive Hold Time WADE/RX-WCLK Inactive Setup Time WE/WY-WCLK Active Setup Time Symbol tWCLK tWWCLH tWWCLL tWAS tWAH tWADH tWADS tWTRS tWTRH tWTDH tWTDS tWXAS tWXAH tWYAS tWYAH tSWE tWES tWEH tWEDH tWEDS tIES tIEH tIEDS tIEDH tDS tDH tWRS tWRH tWRDH tWRDS tWINS tWINH tWINDH tWINDS tWRXS tWRXH tWRXDH tWRXDS tWRYS Min. 50 15 15 5 7 7 7 5 7 7 7 5 7 5 7 5000 5 7 7 7 5 7 7 7 5 15 5 7 7 7 5 7 7 7 5 7 7 7 5 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor AC Characteristics (2/4)
MSM548333
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter WE/WY-WCLK Active Hold Time WE/WY-WCLK Inactive Hold Time WE/WY-WCLK Inactive Setup Time RCLK Cycle Time RCLK "H" Pulse Width RCLK "L" Pulse Width RR1/TR-RCLK Active Setup Time RR1/TR-RCLK Active Hold Time RR1/TR-RCLK Inactive Hold Time RR1/TR-RCLK Inactive Setup Time RXINC1-RCLK Active Setup Time RXINC1-RCLK Active Hold Time RXINC1-RCLK Inactive Hold Time RXINC1-RCLK Inactive Setup Time RADE1/RX-RCLK Active Setup Time RADE1/RX-RCLK Active Hold Time RADE1/RX-RCLK Inactive Hold Time RADE1/RX-RCLK Inactive Setup Time RE1/RY-RCLK Active Setup Time RE1/RY-RCLK Active Hold Time RE1/RY-RCLK Inactive Hold Time RE1/RY-RCLK Inactive Setup Time Y1 and C1 Read Port Output Instruction Setup Time Y1 and C1 Read Port Output Instruction Hold Time Y1 and C1 Read Port Output Instruction Inactive Hold Time Y1 and C1 Read Port Output Instruction Inactive Setup Time Y1 and C1 Read Port Read EnableTime Y1 and C1 Read Port Read Data Hold Time Y1 and C1 Output Access Time Y1 and C1 Data Output Turn Off Delay Time RR2/TR-RCLK Active Setup Time RR2/TR-RCLK Active Hold Time RR2/TR-RCLK Inactive Hold Time RR2/TR-RCLK Inactive Setup Time RXINC2-RCLK Active Setup Time RXINC2-RCLK Active Hold Time RXINC2-RCLK Inactive Hold Time RXINC2-RCLK Inactive Setup Time RADE2/RX-RCLK Active Setup Time Symbol tWRYH tWRYDH tWRYDS tRCLK tWRCLH tWRCLL tRRS1 tRRH1 tRRDH1 tRRDS1 tRINS1 tRINH1 tRINDH1 tRINDS1 tRRXS1 tRRXH1 tRRXDH1 tRRXDS1 tRRYS1 tRRYH1 tRRYDH1 tRRYDS1 tRES1 tREH1 tREDH1 tREDS1 tSRE1 tOH1 tAC1 tOHZ1 tRRS2 tRRH2 tRRDH2 tRRDS2 tRINS2 tRINH2 tRINDH2 tRINDS2 tRRXS2 5 7 7 7 5 7 7 7 5 Min. 7 7 7 30 12 12 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7 5 tAC1 7 7 5000 15 \ 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor AC Characteristics (3/4)
MSM548333
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter RADE2/RX-RCLK Active Hold Time RADE2/RX-RCLK Inactive Hold Time RADE2/RX-RCLK Inactive Setup Time RCLKY2 Cycle Time RCLKY2 "H" Pulse Width RCLKY2 "L" Pulse Width REY2/RY-RCLK Active Setup Time REY2/RY-RCLK Active Hold Time REY2/RY-RCLK Inactive Hold Time REY2/RY-RCLK Inactive Setup Time Y2 Read Port Output Instruction Setup Time Y2 Read Port Output Instruction Hold Time Y2 Read Port Output Instruction Inactive Hold Time Y2 Read Port Output Instruction Inactive Setup Time Y2 Read Port Enable Time Y2 Read Port Read Data Hold Time Y2 Output Access Time Y2 Data Output Turn Off Delay Time RCLKC2 Cycle Time RCLKC2 "H" Pulse Width RCLKC2 "L" Pulse Width REC2/RY-RCLK Active Setup Time REC2/RY-RCLK Active Hold Time REC2/RY-RCLK Inactive Hold Time REC2/RY-RCLK Inactive Setup Time C2 Read Port Output Instruction Setup Time C2 Read Port Output Instruction Hold Time C2 Read Port Output Instruction Inactive Hold Time C2 Read Port Output Instruction Inactive Setup Time C2 Read Port Enable Time C2 Read Port Read Data Hold Time C2 Output Access Time C2 Data Output Turn Off Delay Time Y1 and C1 Serial Read Address Input Active Setup Time Y1 and C1 Serial Read Address Input Active Hold Time Y1 and C1 Serial Read Address Input Inactive Hold Time Y1 and C1 Serial Read Address Input Inactive Setup Time Y1 and C1 Serial Read X Address Setup Time Y1 and C1 Serial Read X Address Hold Time Symbol tRRXH2 tRRXDH2 tRRXDS2 tRCLKY tWRCLHY tWRCLLY tRRYSY2 tRRYHY2 tRRYDHY2 tRRYDSY2 tRESY2 tREHY2 tREDHY2 tREDSY2 tSREY2 tOHY2 tACY2 tOHZY2 tRCLKC tWRCLHC tWRCLLC tRRYSC2 tRRYHC2 tRRYDHC2 tRRYDSC2 tRESC2 tREHC2 tREDHC2 tREDSC2 tSREC2 tOHC2 tACC2 tOHZC2 tRAS1 tRAH1 tRADH1 tRADS1 tRXAS1 tRXAH1 Min. 7 7 7 30 12 12 5 7 7 7 5 tACY2 7 7 5000 15 -- 20 30 12 12 5 7 7 7 5 tACC2 7 7 5000 15 -- 20 5 7 7 7 5 7 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor AC Characteristics (4/4)
MSM548333
Measurement Conditions: (VCC = 3.3 V 0.3 V, Ta = 0 to 70C) Parameter Y1 and C1 Serial Read Y Address Setup Time Y1 and C1 Serial Read Y Address Hold Time Y2 and C2 Serial Read Address Input Active Setup Time Y2 and C2 Serial Read Address Input Active Hold Time Y2 and C2 Serial Read Address Input Inactive Hold Time Y2 and C2 Serial Read Address Input Inactive Setup Time Y2 and C2 Serial Read X Address Setup Time Y2 and C2 Serial Read X Address Hold Time Y2 Serial Read Y Address Setup Time Y2 Serial Read Y Address Hold Time C2 Serial Read Y Address Setup Time C2 Serial Read Y Address Hold Time Transition Time (Rise and Fall) Symbol tRYAS1 tRYAH1 tRAS2 tRAH2 tRADH2 tRADS2 tRXAS2 tRXAH2 tRYASY2 tRYAHY2 tRYASC2 tRYAHC2 tT Min. 5 7 5 7 7 7 5 7 5 7 5 7 3 Max. -- -- -- -- -- -- -- -- -- -- -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note :
Measurement conditions Input pulse level Input timing reference level Output timing reference level Input rise/fall time Load condition
: VIH = VCC - 0.3 V, VIL = 0.5 V : VIH = VCC - 0.3 V, VIL = 0.5 V : VOH = 2.2 V, VOL = 0.7 V : 3 ns : CL = 30 pF (Oscilloscope and tool capacity included)
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Semiconductor
Write Cycle (Address Setting Cycle)
TIMING WAVEFORM
tWCLK tWWCLL WCLK tWWCLH WADE/RX tWADH tWXAS tWXAH Valid A8 tWAS tWAH tWADS
WXAD
WYAD
WE/WY
, , ,
Valid A1 Valid A0 tWYAS tWYAH Valid B9 Valid B8 Valid B1 Valid B0 tSWE tWEDH tWES tIEDH tIES Low Low
IE
WR/TR
WXINC
MSM548333
tDS tDH Valid
tDS tDH Valid
DINY/0 - 7 DINC/0 - 3
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Semiconductor Write Cycle (WE Control)
(N-2)CYCLE (N-1)CYCLE \ WCLK \ \ WADE/RX \ \ IE \ \ WR/TR \ \ WXINC \ \ \ \ \ WE/WY tWEH tWEDS tWEDH tWES N CYCLE tWCLK
MSM548333
(N+1) CYCLE (N+2) CYCLE
Low High
Low
Low

DINY/0 - 7 DINC/0 - 3
Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N) Valid D(N+1) Valid D(N+2)
Note : In the WE/WY = "L" cycle, the write address pointer is not incremented and no DIN data is written. Write Cycle (IE Control)
\ \
(N-2)CYCLE (N-1)CYCLE
N CYCLE
tWCLK
(N+2) CYCLE (N+3) CYCLE
WCLK
\ \ \ \
WADE/RX
Low
High
WE/WY
\ \
WR/TR
Low
\ \ \
WXINC
Low
tIEH
tIEDS tIEDH
tIES
IE \ DINY/0 - 7 DINC/0 - 3 \ \
Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N) Valid D(N+2) Valid D(N+3)
Note : In the IE = "L" cycle, the write address pointer is incremented, though no DIN data is written and the memory data is held.
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Semiconductor Write Cycle (Write Transfer)
(N-2)CYCLE (N-1)CYCLE \ WCLK \ \ WADE/RX \ \ WR/TR \ \ WXINC \ \ WE/WY \ DINY/0 - 7 DINC/0 - 3 \ \ tWTRS tWTRH tWTDH tWTDS N CYCLE tWCLK
MSM548333
Low
Note : When finishing the write operation on a line, be sure to perform a write transfer operation because the write data on the line is stored in the memory cell.

Low tWEH tWEDS
Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N)
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Semiconductor
Read Cycle (Y1, C1) (Address Setting Cycle)
tRCLK tWRCLL
RCLK
RADE1/RX
RXAD1
RYAD1
RE1/RY
RR1/TR
RXINC1 tAC1 DOY1/0 - 7 DOC1/0 - 3 High-Z Valid tOH1 Valid
, , ,
tWRCLH tRAS1 tRAH1 tRADS1 tRADH1 tRXAS1 tRXAH1 Valid C8 Valid C1 Valid C0 tRYAS1 tRYAH1 Valid D9 Valid D8 Valid D1 Valid D0 tSRE1 tREDH1 tRES1 Low Low
MSM548333
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Semiconductor
Read Cycle (Y2) (Address Setting Cycle)
tRCLK tWRCLL RCLK tWRCLH RADE2/RX tRADH2 tRXAS2 tRXAH2 Valid E8 tRAS2 tRAH2 tRADS2
, , , ,
RXAD2 Valid E1 Valid E0 tRYASY2 tRYAHY2 Valid F9 RYADY2 Valid F8 Valid F1 Valid F0 RR2/TR Low RXINC2 tRCLKY tWRCLLY RCLKY2 tWRCLHY REY2/RY tACY2 DOY2/0 - 7 High-Z tOHY2 Valid Valid tREDHY2 tRESY2 tSREY2 Low
MSM548333
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Semiconductor
Read Cycle (C2) (Address Setting Cycle)
tRCLK tWRCLL
, , , , , , , ,
RCLK tWRCLH tRAS2 tRAH2 tRADS2 RADE2/RX tRADH2 tRXAS2 tRXAH2 Valid E8 RXAD2 Valid E1 Valid E0 tRYASC2 tRYAHC2 Valid F9 RYADC2 Valid F8 Valid F1 Valid F0 RR2/TR Low RXINC2 tRCLKC tWRCLLC RCLKC2 tWRCLHC REC2/RY tACC2 DOC2/0 - 3 High-Z tOHC2 Valid Valid tREDHC2 tRESC2 tSREC2 Low
MSM548333
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Semiconductor Read Cycle (RE Control)
(L-2)CYCLE \ RCLK \ \ RADE1/RX \ \ RR1/TR \ \ RXINC1 \ \ RE1/RY \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ RR2/TR \ \ RXINC2 \ (M-2)CYCLE (M-1)CYCLE \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tOHC2
Valid D(N-3) Valid D(N-2) Valid D(N-1)
MSM548333
(L-1)CYCLE
L CYCLE
tRCLK
(L+1) CYCLE (L+2) CYCLE
Low
Low
Low tREH1 tREDS1 tREDH1 tRES1
tOH1
Valid D(L-3) Valid D(L-2) Valid D(L-1)
tOHZ1
Valid D(L)
tAC1 High-Z
Valid D(L+1) Valid D(L+2)
\ \ \
Low
Low
Low M CYCLE tRCLKY (M+1) CYCLE (M+2) CYCLE
tREHY2 tREDSY2 tREDHY2 tRESY2
tOHY2
Valid D(M-3) Valid D(M-2) Valid D(M-1)
tOHZY2
Valid D(M)
tACY2 High-Z
Valid D(M+1) Valid D(M+2)
(N-2)CYCLE (N-1)CYCLE
N CYCLE
tRCLKC
(N+1) CYCLE (N+2) CYCLE
tREHC2 tREDSC2 tREDHC2 tRESC2
tOHZC2
Valid D(N)
tACC2 High-Z
Valid D(N+1) Valid D(N+2)
Note : In the cycle in which RE1/RY = "L", REY2/RY = "L", or REC2/RY = "L", the read address pointer is not incremented and the output enters the high impedance state. The signals RE1/RY, REY2/RY, and REC2/RY can be operated independently.
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Semiconductor Write Reset (1) Mode
tWCLK tWWCLL
MSM548333
\ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC DINY/0 - 7 DINC/0 - 3 \ \ \
Note : Both the line address and word address are reset to 0.
Write Reset (2) Mode
,,,,
tWWCLH tWRXDH tWRXS tWRXH tWRXDS tSWE tWRDH tWRS tWRH t WRDS tDS tDH Valid Low tDS tDH Valid tWCLK tWWCLL tWWCLH tWRXDH tWRXS tWRXH tWRXDS tSWE tWRDH tWRS tWINDH tWINS tWRH t WRDS tWINH t
WINDS
\ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \ Valid \ Valid tDS tDH
Low tDS tDH
Note : Both the line address and word address are reset to 0. However, since the internal address register is also reset to 0, the initialized address data is cleared.
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Semiconductor Write Line Increment (1) Mode
tWCLK tWWCLL \ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \ \ tDS tDH Valid tWINDH tWINS tWINH t
WINDS
MSM548333
tWWCLH
tSWE tWRDH tWRS tWRH t WRDS
Note : The line address is incremented by 1 and the word address is reset to 0.
Write Line Increment (2) Mode
tWCLK tWWCLL
\ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \

Valid tWWCLH tSWE tWRYDH tWRYS tWRYH tWRYDS tWRDH tWRS tWRH t WRDS tWINDH tWINS tWINH t
WINDS
Low tDS tDH
tDS tDH Valid
Low tDS tDH Valid
\
Note : The line address is incremented by 1 and the word address is reset to the initialized address.
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Semiconductor Write Reset (3) Mode
tWCLK tWWCLL \ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \ \ tDS tDH Valid tSWE tWRDH tWRS tWRH t WRDS tWRYDH tWRYS tWRYH tWRYDS tWWCLH tWRXDH tWRXS tWRXH tWRXDS
MSM548333
Low
Note : The line address is reset to 0 and the word address is reset to the initialized address.
Write Line Hold (2) Mode
\ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \

tDS tDH Valid tWCLK tWWCLL tWWCLH tSWE tWRYDH tWRYS tWRYH tWRYDS tWRDH tWRS tWRH t WRDS tDS tDH Valid Low tDS tDH Valid
\
Note : The line address is held and the word address is reset to the initialized address.
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Semiconductor Write Address Jump Mode
tWCLK tWWCLL \ WCLK \ \ WADE/RX \ \ WE/WY \ \ WR/TR \ \ WXINC \ DINY/0 - 7 DINC/0 - 3 \ \ tSWE tDS tDH Valid tWINDH tWINS tWINH t
WINDS
MSM548333
tWWCLH tWRXDH tWRXS tWRXH tWRXDS tWRYDH tWRYS tWRYH tWRYDS tWRDH tWRS tWRH t WRDS
Note : Both the line address and word address are reset to the initialized addresses.

Valid
Low tDS tDH
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Semiconductor Read Line Hold (1) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRRDH1 tRRS1 tRRH1 tRRDS1 tSRE1 tREDH1 tRES1 tWRCLH
MSM548333
Low
Note : The line address is held and the word address is reset to 0.
,,
High-Z tRRDH2 tRRS2 tRRH2 t RRDS2 tSREY2 tREDHY2 High-Z tSREC2 tREDHC2 High-Z
Low tAC1 tOH1 Valid Valid
Low
Low tRCLKY tWRCLLY tRESY2 tWRCLHY
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
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Semiconductor Read Reset (1) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRRDH1 tRRS1 tRRH1 tRRDS1 tSRE1 tREDH1 tRES1 tWRCLH tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
MSM548333
Note : Both the line address and word address are reset to 0.
,,
High-Z tRRXDH2 tRRXS2 tRRXH2 t
RRXDS2
Low tAC1 tOH1 Valid Valid
tRRDH2 tRRS2
tRRH2 t RRDS2
Low tRCLKY tWRCLLY tRESY2 tWRCLHY
tSREY2
tREDHY2
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
High-Z
tSREC2
tREDHC2
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
High-Z
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Semiconductor Read Reset (2) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRINDH1 tRINS1 tRINH1 tRINDS1 tAC1 tOH1 Valid tRRDH1 tRRS1 tRRH1 tRRDS1 tSRE1 tREDH1 tRES1 tWRCLH tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
MSM548333
Note : Both the line address and word address are reset to 0. However, since the internal address register is also reset to 0, the initialized address data is cleared.
,,
High-Z tRRXDH2 tRRXS2 tRRXH2 t
RRXDS2
Valid
tRRDH2 tRRS2
tRRH2 t RRDS2
tRINDH2 tRINS2 tRINH2 tRINDS2
tRCLKY tWRCLLY tRESY2 tWRCLHY
tSREY2
tREDHY2
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
High-Z
tSREC2
tREDHC2
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
High-Z
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Semiconductor Read Line Increment (1) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRINDH1 tRINS1 tRINH1 tRINDS1 tAC1 tOH1 Valid tRRDH1 tRRS1 tRRH1 tRRDS1 tSRE1 tREDH1 tRES1 tWRCLH
MSM548333
Low
Note : The line address is incremented by 1 and the word address is reset to 0.
,,
High-Z tRRDH2 tRRS2 tRRH2 t RRDS2 tRINDH2 tRINS2 tRINH2 tRINDS2 tSREY2 tREDHY2 High-Z tSREC2 tREDHC2 High-Z
Valid
Low
tRCLKY tWRCLLY tRESY2 tWRCLHY
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
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Semiconductor Read Line Increment (2) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRINDH1 tRINS1 tRINH1 tRINDS1 tAC1 tOH1 Valid tRRDH1 tRRS1 tRRH1 tRRDS1 tRRYDH1 tRRYS1 tRRYH1 t
RRYDS1
MSM548333
tWRCLH tSRE1 Low tREDH1 tRES1
Note : The line address is incremented by 1 and the word address is reset to the initialized address.
,,
High-Z tRRDH2 tRRS2 tRRH2 t RRDS2 tRINDH2 tRINS2 tRINH2 tRINDS2 tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2 tREDHY2 tSREY2 High-Z tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2 tREDHC2 tSREC2 High-Z
Valid
Low
tRCLKY tWRCLLY tRESY2 tWRCLHY
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
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Semiconductor Read Reset (3) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRRDH1 tRRS1 tRRH1 tRRDS1 tRRYDH1 tRRYS1 tRRYH1 tRRYDS1 tREDH1 tRES1 tWRCLH tRRXDH1 tRRXS1 tRRXH1 tRRXDS1
MSM548333
Low
Note : The line address is reset to 0 and the word address is reset to the initialized address.
,,
tSRE1 High-Z tRRXDH2 tRRXS2 tRRXH2 t tRRS2
RRXDS2
tAC1
tOH1 Valid Valid
Low
tRRDH2
tRRH2 t RRDS2
tRCLKY tWRCLLY tRESY2 tWRCLHY
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tREDHY2
tSREY2 High-Z
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tREDHC2
tRESC2
tWRCLHC
tSREC2 High-Z
tACC2
tOHC2 Valid Valid
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Semiconductor Read Line Hold (2) Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ RXINC1 \ DOY1/0 - 7 DOC1/0 - 3 RADE2/RX \ \ \ \ \ RR2/TR \ \ RXINC2 \ \ RCLKY2 \ \ REY2/RY \ \ DOY2/0 - 7 \ \ RCLKC2 \ \ REC2/RY \ \ DOC2/0 - 3 \ tRRDH1 tRRS1 tRRH1 tRRDS1 tRRYDH1 tRRYS1 tRRYH1 t
RRYDS1
MSM548333
tWRCLH tSRE1 Low tREDH1 tRES1
Note : The line address is held and the word address is reset to the initialized address.
,,
High-Z tRRDH2 tRRS2 tRRH2 t RRDS2 tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2 tREDHY2 tSREY2 High-Z tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2 tREDHC2 tSREC2 High-Z
tAC1
tOH1 Valid Valid
Low
tRCLKY tWRCLLY tRESY2 tWRCLHY
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
tRESC2
tWRCLHC
tACC2
tOHC2 Valid Valid
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Semiconductor Read Address Jump Mode
tRCLK tWRCLL \ RCLK \ \ RADE1/RX \ \ RE1/RY \ \ RR1/TR \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ tRRDH1 tRRS1 tRRH1 tRRDS1 tRINDH1 tRINS1 tRINH1 tRINDS1 tRRYDH1 tRRYS1 tRRYH1 t
RRYDS1
MSM548333
tWRCLH tRRXDH1 tRRXS1 tRRXH1 tRRXDS1 Low tREDH1 tRES1
,,
RXINC1 DOY1/0 - 7 tSRE1 High-Z tAC1 DOC1/0 - 3 RADE2/RX tRRXDH2 tRRXS2 tRRXH2 t tRRS2
RRXDS2
tOH1 Valid Valid
Low
tRRDH2
tRRH2 t RRDS2
RR2/TR
tRINDH2 tRINS2 tRINH2 tRINDS2
RXINC2
tRCLKY tWRCLLY tWRCLHY
RCLKY2
tRRYDHY2 tRRYSY2 tRRYHY2 tRRYDSY2
tREDHY2
tRESY2
REY2/RY
DOY2/0 - 7
tSREY2 High-Z
tACY2
tOHY2 Valid Valid tRCLKC tWRCLLC
RCLKC2
tRRYDHC2 tRRYSC2 tRRYHC2tRRYDSC2
tREDHC2
tRESC2
tWRCLHC
REC2/RY
DOC2/0 - 3
tSREC2 High-Z
tACC2
tOHC2 Valid Valid
Note : Both the line address and word address are reset to the initialized addresses.
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Semiconductor
MSM548333
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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